Carlo Marcelo Arenas Belón
Carlo Marcelo Arenas Belón
> > > > To me it seems `p->pcre2_jit_on = 0;` should happen when `jitret` is not 0, not `die`. > > > > > > https://public-inbox.org/git/[email protected]/ would be the...
If the objective is to clean up the code, then there is little benefit by dropping MIPS III and would need instead to drop everything before `r2` which is IMHO...
RBIT seems to be available for ARMv7 and ARMv6 with Thumb2, but test79 case 21 failed with soft-float ABI in Thumb2, althought that might be an independent issue as it...
> Is this still incomplete? yes; armv6k is the minimum (so not all armv6 systems will work), and specifically haven't been able to either confirm or deny if the original...
FWIW; thanks[1] to the NetBSD community, we know next release of PCRE2 is most likely going to work fine (at least in NetBSD 10) for the most common RaspberryPI that...
the bug is triggered by case 5, so probably `SLJIT_SIMD_MEM_ALIGNED_16` might not be supported, at least in this CPU: https://github.com/zherczeg/sljit/blob/f6326087b3404efb07c6d3deed97b3c3b8098c0c/test_src/sljitTestSimd.h#L142-L147 the [documentation](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-memory-alignment-constraints) for RVV mentions: >Implementations are allowed to raise...
FWIW, gcc 14.2.0 also triggers a Bus error, but [next](https://gcc.gnu.org/pipermail/gcc-patches/2024-May/652931.html) version seems to default to NOT allow misaligned loads unless it was requested.
> I remember riscv was proud that misaligned memory support is always available. Not sure if I would qualify it as "proud", but the `Zicclsm` extension that is mandatory for...
something that might be interesting would be to mix this logic with some other CPU specific codepaths that could be dynamically patched in. I am sure (for example) that in...
> but there is no way I know of to have a call which says "only follow symlinks if they stay within a subtree" without a race condition. there is...