Instruction details for RISC-V

[chiffreKing]

Hello,

for ARM instructions there are the details wether a register is accessed by a writing or reading operation the same applies for memory operations. An example for that can be seen below made with the cs tool for ARM Thumb code. You can see the .type (REG or MEM) and the .access (WRITE or READ) information:

Thumb instruction:

0  64 48  ldr    r0, [pc, #0x190]     ID: 83 (ldr)     op_count: 2         operands[0].type: REG = r0         operands[0].access: WRITE         operands[1].type: MEM             operands[1].mem.base: REG = pc             operands[1].mem.disp: 0x190         operands[1].access: READ     Registers read: pc     Registers modified: r0     Groups: thumb thumb1only 

Trying the same for RISC-V architecture results in that:

RISC-V instruction:

0  13 0d 4d 00  addi    s10, s10, 4     ID: 2 (addi)     op_count: 3         operands[0].type: REG = s10         operands[1].type: REG = s10         operands[2].type: IMM = 0x4

The .access information are missing. I figured out that this is due to a missing file in the RISC-V folder. ARM has instruction operand mapping (found here RISC-V doesn't.

Is anyone aware of a fork that implements that or did anyone find a solution for that?

Thanks already, your help is appreciated.

[Rot127]

We currently finish a huge update feature (https://github.com/capstone-engine/capstone/pull/1949). One of the succession PRs, which handles RISC-V, will add the access information.

[chiffreKing]

That's great!! Have you an idea when the Update will be released?

[Rot127]

Not really. PPC comes after ARM and then we have to whats next. But I'll write enough documentation about it so you can do the update itself if you have the time.