capstone
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capstone-engine
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webass...
## What is Auto-Sync ? Capstone Auto-Sync is an initiative to partly automate the synchronization of certain architectures to the latest. Most of the Capstone's `.inc` files a generated from...
This work is based on #1803. Note that only MIPS is included in this PR. As that's the arch which I most familiar. I'll work on RISC-V, sparc and others...
The `BO` and `BI` field in PPC branch opcodes determine: `BO`: if the `ctr` register is altered or a `cr` register field is checked. `BI`: holds the offset of the...
This issue will track the changes required to support the disassembly of RISC-V (www.riscv.org) instruction set. I will start with the support for RV64 first and then add the support...
The title says it all, how could it be fixed without the need to compile capstone myself?
The work done is this pull request updates the AArch64 disassembler to Armv9.2-a; based upon LLVM 14.0.5. Detailed below is a summary of changes made : - New `.inc` files...
### Brief The PPC instruction `mtocrf` should have two operands: register `RS` and immediate `fxm`. But Capstone only decodes the register. ### Reproduce ```bash > ./cstool -d ppc64be 7c120120 0...
Instructions like vldrw.u32 q1, [r1] comes out as and `ldc` instruction. The decoding doesn't seem to recognise the fields that distinguish them.
**Environment information** * Version: 4.0.2 * Operating System: Linux * Obtained from: python3 pip **Test code** ``` python # vmovups zmm1, zword ptr [r13 + r12*4] # ret CODE =...
Paired Singles is an vector instruction set extension for PowerPC, developed as a lightweight alternative to AltiVec, only dealing with two single precision floats at a time. The extension was...
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Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webass...