Mark std_bit_slice and more std_ops as combinational; std_bit_slice bug fixed.

[abnerhexu]

This pull request has two contributions.

1. As #2292 mentioned, some ops are combinational but are not marked in Python is_comb() function.

2. Fixed bugs in std_bit_slice verilog template and doc, since in verilog a signal's slice [a:b] contains both a-th bit and b-th bit.

[rachitnigam]

Hm, looks like the tests are failing. Can you take a look and fix them?

[abnerhexu]

Yep, I'm looking for what is happening.

[rachitnigam]

@abnerhexu any progress on this?

[ekiwi]

I think the change to the Verilog implementation of the slice operation is going to cause problems. We actually followed the Verilog implementation when implementing slice in cider and there are quite some benchmarks that rely on the current implementation. I think it would make sense to just update the doc comments and leave the implementation as it is.

[rachitnigam]

@ekiwi that sounds reasonable too!

[abnerhexu]

I think the change to the Verilog implementation of the slice operation is going to cause problems. We actually followed the Verilog implementation when implementing slice in cider and there are quite some benchmarks that rely on the current implementation. I think it would make sense to just update the doc comments and leave the implementation as it is.

Sorry for the late reply.

I got that. Maybe I need to recall a version and just change the combination indicators in frontend Python.

[rachitnigam]

Mistakenly committed the changes to 8d242da68ad5cfb266cd622911beafe341921d3a