WIP: Create a backwards compatible flow for `xo`/`xclbin` generation with Calyx-AXI-wrapper

[nathanielnrn]

At the highest level this PR should allow for correct xclbins to be produced from Calyx programs.

Broadly speaking this PR does 2 things (sorry for combining them, but some small fixes are sprinkled throughout making things hard to separate into their own changes):

1. This PR introduces an axi_controller_generator.py which is meant to create a subordinate adhering to Xilinx's control spec. There might be some issues with this as executing on hardwares seems to hang at the moment, and the only difference between the generated verilog is the addition of the controller subordinate AFAIK.
2. Adds some fud2 functions to go from verilog to a .xo. This is different from the previous .futil to .xo (which should eventually be deprecated), and is the "correct" way to create a .xo with the new Calyx-AXI-wrappers.

I'll do my best to comment the PR heavily to explain which changes affect what.

Furthermore, not sure if the controller itself needs a deep dive w.r.t code review. There are probably problems with it, that require waveform debugging to uncover.

EDIT: More work than I thought regarding backwards compatibility. Commented where changes are needed

In general there are a few outstanding TODOs even after this PR is merged. I'll make issues about these:

• [ ] Update the static wrapper generator to correctly add a Xilinx control subordinate to the wrapper.
• [ ] Change axi-generator.py to axi_generator.py
• [ ] Test that xclbins get produced correctly with our static wrapper (currently this has mainly been tested on dynamic versions.
• [ ] Figure out why the current dynamic wrapper seems to hang when running on actual hardware (likely an issue with the control subordinate)