Create inline asm support for RISC-V

[chuckb]

I would like to add this capability. After reviewing the source for existing arches, I have a few questions:

1. What registers and/or pseudonyms for registers should be defined in clobbers enumeration? If I look at aarch64, for example, I see registers enumerated with values "r0" - "r31", yet those designations are for aarch32. I do see aarch64 registers defined in arrays below, beginning with $. Help me understand the rationale and the mapping that seems to be going on.

2. What instructions need to be defined in asm_target.c? All in the ISA, broken out between those that clobber registers and those that don't?

Aside from an asm header file with register dfns, and an init function in asm_target.c, plus a few places where I see unsupported traps for RISC-V...is there anything else that needs attn to get this done?