c3lang
Add support for RiscV (ESP) llvm embedded target
Right now we already have elf-riscv32 available, can you experiment a bit with it to see what's missing from the toolchain? Presumably there are other things needed for esp to run, so maybe we could include more out of the box, or at least a tutorial.
I have a few boards on order to try this out on real hardware. There is a video on how I got an example to work under qemu. The compiler required no modifications, but there were a few tricks. I am also working on adding block asm support for RISC-V. I'll submit a PR for consideration when done.
Video: https://youtu.be/0iAJxx6Ok4E
That's really cool. I wonder what the problem was with the linker. Did you use C3's built in linker or an external one? And I guess also that --no-entry should probably be default on targets without an OS provided, e.g. elf-riscv?
Anything else to improve the quality of life?
I was using the external risc-v toolchain linker since I already had a linker file that worked (well, with the minor mod mentioned in the video.) I used no-entry as I was trying to strip everything to bare bones to make sure my own startup and main entry point was followed. It would be cool to not have to use make and use C3's facility, but I had stuff working from other projects I borrowed, so I used what I had. It may indeed work with the right flags.
It would be interesting to see what's needed to fix if you just do --no-entry and --use-libc=no.