c3lang
Add support for Xtensa embedded llvm target
request to add support for the Xtensa llvm embedded target (for esp development boards)
This is currently blocked due to LLVM support of Xtensa is not completely merged yet. This might happen in LLVM 20
This is currently blocked due to LLVM support of Xtensa is not completely merged yet. This might happen in LLVM 20
Q: What is xtensa's relevance for most users? A: esp32 (legacy)!
I have my doubts about that. Maybe LLVM 30+!! Xtensa for LLVM is experimental (generic cpu-features only). Currently need espressif-fork for esp8266, esp32 & esp32-S[2|3].
upstream: https://github.com/llvm/llvm-project/blob/master/llvm/lib/Target/Xtensa/Xtensa.td espressif/llvm https://github.com/espressif/llvm-project/blob/xtensa_release_18.1.2/llvm/lib/Target/Xtensa/Xtensa.td
References
- https://github.com/espressif/llvm-project/issues/4
- https://github.com/ldc-developers/ldc/issues/4725 (similar question)
My simple test (picsimlab/espressif-QEMU)
# static c3c compiler
c3c --version
C3 Compiler Version: 0.6.2 (prerelease)
Installed directory: /home/kassane/.local/bin/
LLVM version: 18.1.2
LLVM default target: x86_64-linux-musl
So what do you advice here?
My proposal is to continue the development of xtensa support, focusing on esp32-devices (primary purpose for espressif users).
Note: New espressif devices, now replacing xtensa to risc-v32 (no SIMD/Vector). Old xtensa (esp32/S[2|3] legacy) for higher performance.
Add c3c using espressif/llvm backend artifact in the CI (no impacting upstream artifacts). This will make upstream c3c accessible without forking (like, esp-rs).
So like a special espressif c3c version?
esp32 support only! The other upstream targets will remain unchanged.
So like a special espressif c3c version?
off-topic
The forked compiler is static musl-libc because it was built using build.zig.
LLVM default target: x86_64-linux-musl