EDIF to Verilog Attempt

[andrewmkeller]

This task involves converting an edif netlist to a structrual verilog netlist. It is considered an attempt because I anticipate a number of things coming up (like names and properties) that will prevent a clean conversion. We want to identify what these issues are and make a plan to resolve them.

[thunder-hammer]

Some things that may be lacking with this feature:

Properties, parameters, constraints will all likely be ignored, The name conversion process could use some more testing, it probably works for the most part Some other information may be lost.

At the very least it would be good to dive in and document things that will be lost.