riscv64: Improve base select lowering

[afonso360]

👋 Hey,

This PR is an attempt at improving the base lowering for the select instruction in the RISC-V backend. It reduces one instruction from the current lowering.

Currently our selects have the following instructions:

b{cond} rc, 0xc
mv rd, rx
j 8
mv rd, ry

With this change we now produce the following:

mv rd, rx
b{cond} rc, 8
mv rd, ry

So, we lose the jump instruction, but one of the moves becomes unconditional. This to me feels like it's worth it, but I have no data to prove one way or the other, and I think if i try to measure it with sightglass it probably won't detect this change.

One of the benefits of this lowering is that now if one of the input registers is the same as the destination register we can do a two instruction select, like so (assuming rx = rd):

b{cond} rc, 8
mv rd, ry

I've had to do some regalloc surgery to make that possible which makes some other cases get worse regalloc.

This is built on top of #8695, but only the last commit is relevant.

[github-actions[bot]]

Subscribe to Label Action

cc @cfallin, @fitzgen

This issue or pull request has been labeled: "cranelift", "cranelift:area:riscv64", "cranelift:meta", "isle"

Thus the following users have been cc'd because of the following labels:

• cfallin: isle
• fitzgen: isle

To subscribe or unsubscribe from this label, edit the .github/subscribe-to-label.json configuration file.

Learn more.

[abrown]

I'm positive toward this change but someone more familiar with RISC-V should probably review this?