[cranelift][x64][arm] Folding fneg + fabs

[MaxGraey]

fneg(fabs(x)) could be possible after copysign(x, -C) -> fneg(fabs(x)) peephole optimization on LLVM / Binaryen, so I guess it's make sense to simplify it further on cranelift during lowering stage.

x64:

orsd xmm0, #0x8000000000000000

ppc:

fnabs 1,1

s390x:

lndbr   %f0,%f0

the rest is preserving fneg + fabs

[jameysharp]

I think this looks like a good candidate to work on after @cfallin's mid-end optimizer work lands.

[akirilov-arm]

While Cranelift does not support the 32-bit Arm architecture, I would like to mention that the armv7 lowering is non-sensical because it operates on general-purpose registers (instead of floating-point ones), unless the code is meant to comply with one of the soft float ABIs and the operations are the first ones in the procedure, so that the input value has not been moved into a floating-point register yet.

[MaxGraey]

@akirilov-arm Thanks for the clarification. I removed the mention of armv7