bytecodealliance
Cranelift: s390x: fix patchable call ABI to not clobber outside clobber-save area.
It turns out that the s390x ABI is special wrt our others: the s390x System-V ABI provides an area to all callees to save clobbered GPRs. However this is only large enough for r6-r15, the callee-saves in the standard ABI.
The implementation implicitly assumed this, and when I adjusted the definition of clobbered registers for the patchable ABI, stating that r0-r15 are clobbered instead, the code happily generated a store-multiple (stmg) instruction that saved too much data in too little space, overwriting other bits of the stack.
Also, the clobber-save/restore sequence code only saved the bottom 64 bits of clobbered vector/float registers (which are 128 bits), implicitly encoding the fact that the SysV ABI specifies only the bottom half as callee-saved.
This PR implements patchable properly on s390x by open-coding the sequences to save all vector registers and r0-r5 in the explicit clobber-save area (still using the SysV-defined one for r6-r15).
Note that this is spun out of #12133, and makes tests pass there, in lieu of hacking up a Cranelift runtest harness for editing patchable code here (the failure would only be observable with large enough code to cause unexpected register clobbers anyway).
Ah, yep, sorry, I forgot that we have 32 vector registers on this platform. Thanks for the review!
I've updated to use STMG / LMG; opting not to try to add vector store/load multiple for now since the encoding isn't there but we can do that as followup if needed. (As we discussed in the Cranelift weekly, this isn't too performance-critical on the callee side; in Wasmtime, at least, the save/restore sequence will execute only when hitting a breakpoint.)