bytecodealliance
Support aliasing registers, e.g. for narrower portions of vector or float registers
A number of architectures require us to reason about aliasing registers; for example:
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On AArch64, the standard (AAPCS) calling convention specifies that the lower half of some vector (128-bit) registers is callee-save and the upper half is caller-save; to correctly handle this without a conservative approximation that forces unnecessary clobber-saves, we need to represent the upper and lower halves as separate registers that alias with the vector registers. (There is a potential workaround for this, but it also involves a regalloc API change, and is hacky.) See bytecodealliance/wasmtime#2228.
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On ARM32, the floating-point register file is organized as an array of 32-bit (single-precision) registers that can also be addressed in pairs as 64-bit (double-precision) registers or 128-bit vector registers. A temporary workaround would be to always allocate the largest (128-bit) unit but this is very wasteful when code operates mostly on 32- or 64-bit FP values.
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Many other architectures also have similar register file arrangements.
Ideally, we should be able to define aliasing in the RealRegUniverse and the allocator should Do The Right Thing automatically. We should also ensure that whatever solution we choose does not pessimize the common case.
