Christian Svensson

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On the PHY side I think this should work: ![image](https://user-images.githubusercontent.com/149442/90698846-1722bd80-e282-11ea-9041-fa1afab42c44.png) And the MAC: ![image](https://user-images.githubusercontent.com/149442/90698869-26a20680-e282-11ea-8a67-e6f4c9e90c55.png) There seems to be need a converter between XGMII DC and Standard, see "XGMII Mapping to...

Framer state will likely **not** be part of the metadata, as this will be driven by observed traffic only. It would be a huge pain to try to align the...

Making the encoder have 4 inputs and 4 memories is probably the easiest to scale up when the other ports are activated. The chip has up to 6.25 MiB block...

Is it because it sends NOS maybe? Probably.

> An FC_Port shall enter the LF2 State when a Link Failure condition is detected. Upon entry into the LF2 > State, the FC_Port shall update the appropriate error counter...

~Ended up going with OL1 which is the link init state as it is allowed to remain in that state indefinitely.~ That fix was not cherry-picked. LF2 is the default...

- [ ] OL1 as state on reset - [ ] Transition to LF2 if `avrx_valid` goes low for R_T_TOV, or SFP reports loss of signal.

It should be possible to re-use the OL1 handling from this dropped patch: [rx_state_ol1_handling.txt](https://github.com/bluecmd/fejkon/files/5203436/rx_state_ol1_handling.txt)

https://www.embedded.com/asynchronous-reset-synchronization-and-distribution-challenges-and-solutions talks a bit about the down-sides of async reset, like the metastability when reset is deasserted.

Alex uses synchronous. The more I read the less I think we should change this right now. It would likely help timing as some combinatorial elements would be removed from...