Add a tool to program Cyclone V FPGA on de10nano board from userspace

[antonionevado]

It adds a new tool to program Cyclone V FPGA found on de10 nano board. From the command line, in Linux user space, this tool accepts an .rbf file and program the FPGA. This tool has the same effect than rebooting the board.

Motivation and Context

Useful for debugging and testing.

Description

Is a new tool, nothing else was modified. A binary is provided for easy use.

The procedure for configuring the FPGA is described in the Cyclone V configuration manual:

1. Set the cdratio and cfgwdth bits of the ctrl register in the FPGA manager registers (fpgamgrregs) to match the characteristics of the configuration image. These settings are dependant on the MSEL pinsinput.

2. Set the nce bit of the ctrl register to 0 to enable HPS configuration.

3. Set the en bit of the ctrl registerto 1 to give the FPGA manager control of the configuration inputsignals.

4. Set the nconfigpull bit of the ctrl registerto 1 to pull down the nCONFIG pin and put the FPGA portion of the device into the reset phase.

5. Poll the mode bit of the stat register and wait until the FPGA enters the reset phase.

6. Set the nconfigpull bit of the ctrl register to 0 to release the FPGA from reset.

7. Read the mode bit of the stat register and wait until the FPGA enters the configuration phase.

8. Clear the interrupt bit of nSTATUS (ns) in the gpio interrupt register (fpgamgrregs.mon.gpio_porta_eoi).

9. Set the axicfgen bit of the ctrl register to 1 to enable sending configuration data to the FPGA.

10. Write the configuration image to the configuration data register (data) in the FPGA manager module configuration data registers (fpgamgrdata). You can also choose to use a DMA controller to transfer the configuration image from a peripheral device to the FPGA manager.

11. Use the fpgamgrregs.mon.gpio_ext_porta registers to monitor the CONF_DONE (cd) and nSTATUS (ns) bits.

12. Set the axicfgen bit of the ctrl register to 0 to disable configuration data on AXI slave.

13. Clear any previous DONE status bywriting a 1 to the dcntdone bit of the DCLK status register(dclkstat) to clear the completed status flag.

14. Send the DCLKs required by the FPGA to enter the initialization phase.

15. Poll the dcntdone bit of the DCLK status register (dclkstat) until it changes to 1, which indicates that all the DCLKs have been sent.

16. Write a 1 to the dcntdone bit of the DCLK status register to clear the completed status flag.

17. Read the mode bit of the stat register to wait for the FPGA to enter user mode.

18. Set the en bit of the ctrl register to 0 to allow the external pins to drive the configuration input signals.

How has this been tested?

It is specific low level code for de10nano board. It has the single functionality of programming the FPGA chip and nothing else.

Types of changes

• [ ] Bug fix (non-breaking change which fixes an issue)
• [x] New feature / Optimization (non-breaking change which adds functionality)
• [ ] Breaking change (fix or feature that would cause existing functionality to not work as expected)

Checklist:

• [ ] My code follows the code style of this project.
• [ ] My change requires a change to the documentation.
• [ ] I have updated the documentation accordingly.

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