Ben Gamari
Ben Gamari
Currently the default `devShell` does not include HLS. I recommend that we either enable it by default or introduce another dev-shell (e.g. `with-ide` or `dev`) that does so.
One of the facets of Clash that I have long struggled with is the treatment of naming top-level ports. Ensuring that the port-naming of a top-level entity remains consistent with...
It is fairly common for single SPI bus to consist of a set of parallel MISO/MOSI lanes (c.f. QSPI FLASH). For instance: * many multi-channel ADCs allow each converter to...
Currently if one configures the `Clash.Cores.SPI.spiMaster` in Mode 0, the end of the transfer will race between CS and the capture clock. Specifically, the produced output will raise CS at...
It turns out that Vivado's block design facility has the annoyingly arbitrary limitation that ports may only be of type `std_logic` or `std_logic_vector`. Unfortunately, this means that VHDL produced by...
With `clash-ghc-1.8.0` and GHC 9.2.8, a simple entity using my [`axi-register` package](https://git.smart-cactus.org/ben/axi-register) builds fine when built in conjunction with `axi-register` in a single compilation: ``` $ clash --vhdl Test.hs -isrc...
I have found that value combo box of the "Find by attribute value" interface tends to be far too narrow to accommodate the full text of my attribute values. It...
It may be useful to allow the user to "freeze" all nodes but a selection for the purposes of force-layout. Coupled with #62, this would allow the user to guide...
I have found that the force layout tends to frequently get stuck in local optima when processing my graphs (namely, [heap graphs](https://en.wikipedia.org/wiki/Memory_management#HEAP) when characterising software behavior). I have found that...
It would be useful to be able to guide the force layout engine to emphasize some edges over others. For instance, one might imagine being able to use a edge...