Benjamin Thiemann

Results 14 issues of Benjamin Thiemann

**Environment** VHDL Style Guide (VSG) version: 3.31.0 **Describe the bug** The second assignment in the example below does not align the second line to the space after the assignment operator....

bug

When checking out the instantiation (generic/port map) rules, I noticed that there are some port map rules that do not have a generic map counterpart rule: - `port_map_009` (multiple port...

enhancement

**Environment** VHDL Style Guide (VSG) version: 3.31.0 **Describe the bug** I think this might be related to #1418. A comment at the end of a scope is indented to the...

bug