Add constraints

[vmayoral]

Please do not merge

This PR aims to add functionality to add .xdc files to impose constraints on selected designs however both of the approaches attempted failed (read_xdc and create_fileset) with outputs like:

...
INFO: [HLS 200-10] Setting target device to 'xc7z020clg400-1'
invalid command name "create_fileset"
    while executing
"create_fileset -constrset my_constraints"
    (file "run_hls.tcl" line 9)
    invoked from within
"source [lindex $::argv 1] "
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 { source [lindex $::argv 1] } "
...

Current branch allows to experiment with other alternatives. @benjmarshall, anything that comes to mind when reading this?

[benjmarshall]

Hi, thanks for the contribution. I'll try an get a look at this over the next few days and provide some further input!

[benjmarshall]

I've looked into the specifics of this a bit more and i think it sounds like what you are trying to do is a little outside the scope of HLSCLT. The commands you mention - "read_xdc" and "create_fileset" don't exists as valid Vivado HLS tcl commands as far as I can tell. They are included in the tcl reference manual for the main Vivado tool.

From digging into the Vivado HLS User Guide again I have read that whilst the HLS tool can supply post-synthesis estimates of clock speed and and resource usage, the synthesis results are generally not packaged up and exported, instead it is expected that a downstream tool will be responsible for synthesis either of the design as an IP core, or within a larger design.

Can you give me any more info about your intended use case, or the design flow that you use or would like to achieve? It might be that we can work on bringing in some sort of better integration to a back end Vivado based synthesis stage?