verilog-vcd-parser
verilog-vcd-parser copied to clipboard
Published
20 hours ago •
ben-marshall
ben-marshall
Unable to handle 2D array signals?
Fail to handle such definition in a scope (regs[0] ==> [[[reg[63:0] regs[31:0];]]] is the register file in CPU core)?
line 1663 of wave.vcd: $var wire 64 j, regs[0] [63:0] $end
$var wire 64 ~, regs[10] [63:0] $end
$var wire 64 "- regs[11] [63:0] $end
Parsing~/wave.vcd line 1663 : syntax error, unexpected TOK_DECIMAL_NUM, expecting TOK_KW_END Parse Failed.
