verilog-vcd-parser

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Fail to handle such definition in a scope (regs[0] ==> [[[reg[63:0] regs[31:0];]]] is the register file in CPU core)? line 1663 of wave.vcd: $var wire 64 j, regs[0] [63:0] $end...

secure-v

Parsing multiple files

2

In `scan_end` function, the lexer state was popped. However in `scan_begin`, it was not pushed. Initially, I was thinking this should be okay. But it turned out that if I...

zhanghongce

The latest version doesn't seem to recognize escaped identifiers.

2

Consider this example: ``` $scope module top $end $var wire 1 (C \$procdff$4.Q[2] $end $var wire 1 (D \$procdff$4.Q[1] $end $var wire 1 (E \$procdff$4.Q[0] $end $var wire 1 (G...

RonxBulld

I had just one error from the compiler which I eliminated with a simple change to the Makefile (line 17) from: `CXXFLAGS += -I$(BUILD_DIR) -I$(SRC_DIR) -g -std=c++0x` to: `CXXFLAGS +=...

buttim

Some fixes (Time Datatype, parsing floats, crash when loading 2 files)

1

First of all: Sorry, I don't have time to really turn this into a proper PR at the moment. I stumbled upon this library a few days back, because I...

michi7x7

Parser failed with the following VCD line: ```$var wire 1 - D [3] $end``` Reason was that VCDScanner.l contained the following: ```SCOPE_IDENTIFIER [a-zA-Z_][a-zA-Z_0-9\(\)]+``` Changing this to: ```SCOPE_IDENTIFIER [a-zA-Z_][a-zA-Z_0-9\(\)]*``` Fixed the...

udif