Parse failed

[elliottcstr]

Issue Description

Parse failed on Verilog file/module

What should happen:

There should be no error

What actually happens:

verilog-parser$ ./build/release/src/parser ../add.v
../add.v line 21 - ERROR: syntax error, unexpected KW_TRI1
- 'tri1'
 - Parse failed

Steps to re-create:

// add.v
module add (
        cin,
        dataa,
        datab,
        cout,
        result);
input   cin;
input   [7:0] dataa;
input   [7:0] datab;
output  cout;
output  [7:0] result;


wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
assign unknown = 1'bx;

tri1 devclrn;
tri1 devpor;
tri1 devoe;

endmodule

$> make clean
$> make all
$> make debug
$> ./build/debug/src/parser add.v

---

People to Notify:

• @ben-marshall

Related Issues:

[ben-marshall]

Hi @elliottcstr

Cheers for this one too. The transistor level / trigate part of the syntax is one of the porest tested; it's hard to get real-world examples, and the trivial ones I include in the test suite clearly don't cut it.

Like I said in #27, I'm affraid I don't have time to commit to this, but am very happy accepting pull requests. The project is in something of a mothball state at the moment until I pluck up the courage to do something about it.

[elliottcstr]

@ben-marshall

Roger that. I understand. Just wanted to document for onlookers.