bartokon

Decision trees can get stuck in local minimum. We could make some border cases for search and try to offset the problem.

For now, I think, we should analyze pyrtl feedback with critical times and group wires to distinct speed categories (time delay categories) and put registers there for example: https://machinelearningmastery.com/clustering-algorithms-with-python/ K-Meas?...

Aaaahhh, okay now I know how it works. I thought that you analyze on netlist level, and if you are pipelineing a netlist it could be directly inserted into fpga...

> Better not to reinvent the wheel https://github.com/MattRighetti/leiserson-retiming/wiki Haha can't wait for new pipelinec v2 :D

 [artix_times.txt](https://github.com/JulianKemmerer/PipelineC/files/7612464/artix_times.txt)  [nextpnr_times.txt](https://github.com/JulianKemmerer/PipelineC/files/7612465/nextpnr_times.txt)

Hello, I like using parameters in my IP's. It is possible to type function like: fun(ap_bit a, ap_bit b){} where "8" is a IP core parameter that could be changed,...

Good idea for next stages of the project aka ultra fine tuning. BTW. synth tools should infer regs automatically. We could set lut for some fpga architecture and search for...

I think most of the time FPGA support (right now) 3/2 luts or 6/1. Anyway if we could perform opt by putting registers after it uses 3 input function that...

Hiho, here are the times for artix implementation mypipeline. (Yea I left my PC for more than 8h of synth xD) [artix_times.txt](https://github.com/JulianKemmerer/PipelineC/files/7574996/artix_times.txt)  . We need to extract worst paths...

And this is for Yosys+nextpnr (This graph looks so broken...) LFE5UM5G-85F-8BG756C  [nextpnr_times.txt](https://github.com/JulianKemmerer/PipelineC/files/7575016/nextpnr_times.txt) )