openfpga
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Implement post-PAR timing analysis
Static is preferred, topological would be OK probably. Needs timing data that is not currently released by Silego. Will need to characterize or get them to publish it.
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<azonenberg_work> [Blinky] has a stateful feedback loop in a fabric-based (vs hard IP) counter <azonenberg_work> but my timing analyzer thinks everything is combinatorial right now <azonenberg_work> it tries to trace D to Q combinatorially