Axel Heider
Axel Heider
> Is the `rdtime` instruction handled in software??? That would explain the 2 us, but seems unlikely to me. In general, It depends on the RISC-V hardware if this is...
> This is incredibly stupid for a new platform. I assume they just decided to implement the cycle counter in hardware for the first silicon(s), but no dedicated timer to...
> seL4 can't use the cycle count on riscv, as it misses the guarantees that rdtime/CSR_TIME give, which is that it's synchronised across cores and won't overflow. That is true,...
What is the state of this PR now, can it be merged. Seem it bringe more benefit than harm, if specific platform have issues these could be solved individually then....
> Hello @axel-h could you add a bit context in your commit message? What does "proper" mean? My guess is "generic" means "OpenSBI"? @yyshen We are trying to get it...
Turns out https://github.com/riscv/opensbi/commit/26998f3d116992ae3fc6670c8f724bcc630d33fd is the change where `sifive/fu540` becomes `generic`. The seL4 manifest file currently uses the commit of the v0.9 OpenSBI release, which is before this commit.
Do not merge this unless there is a plan to update OpenSBI to post-v0.9. We are currently using the `master` here, but so far have not found a really strong...
deleted branch by accident
The PR is a draft now. Once OpenSBI releases a new version or there is a good reason to pick an intermediate version we can merge this.
https://github.com/seL4/sel4test-manifest/pull/13 should be merged first.