usbcorev
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Published
20 hours ago •
avakar
avakar
A full-speed device-side USB peripheral core written in Verilog.
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usbcorev issues
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@avakar Would you be able to add some code comment / documentation on the [purpose of some top-level signals](https://github.com/avakar/usbcorev/blob/master/usb.v#L1-L29) ? otherwise user would need to dive into your internals of...
This adds a core description file for the usbcorev core that exposes targets for linting and for building a GDSII using OpenLANE. All targets are also implemented as Github actions...
