Add PAC for ATSAML22J18A

[tahnok]

Very WIP, just want to put this up early to check if this would be accepted at all for this particular chip. Can someone confirm? If yes I'll clean up this PR, see if I can actually build it, etc...

Initial commit of svd2rust for the ATSAML22J18A. Had to modify the SYNCBUSY register definition by hand so that each clock had 1 bit.

Summary

[describe your changes here]

Checklist

• [ ] CHANGELOG.md for the BSP or HAL updated
• [ ] All new or modified code is well documented, especially public items
• [ ] No new warnings or clippy suggestions have been introduced (see CI or check locally)

If Adding a new Board

• [ ] Board CI added to crates.json
• [ ] Board is properly following "Tier 2" conventions, unless otherwise decided to be "Tier 1"

If Adding a new cargo feature to the HAL

• [ ] Feature is added to the test matrix for applicable boards / PACs in crates.json

[bradleyharden]

@tahnok, I think we're open to the idea of supporting more chips, but we've also been short on maintainers lately. This is also the second request to support another chip in just a few days (see #659 and #662). It also comes as I'm trying to port #450 to our other chips, and this is just adding to that effort. We'll have to evaluate and see.

[TethysSvensson]

@bradleyharden How is the workload on the maintainers these days? Would you be interested in accepting this now if this was a bit more finished?