Atish Patra

It was agreed that hypervisor guard hole is not required for RISC-V. Here is the relevant discussions happened last year. https://lists.riscv.org/g/tech-unixplatformspec-archive/search?q=guard+hole We can close this issue if nobody else objects...

The the mailing list is usually available to public. However, this was archived. That's why, it was not available to public. I can check with you Stephano if there is...

We did not have a PRS meeting last week due to holidays in India. It is on next week's meeting agenda. I will update the summary after the meeting.

We already have a SBI extension proposal close to the final stages. It started with misaligned delegation and expanded to other config behaviors for ISA (ADUE, CFI etc). https://lists.riscv.org/g/tech-prs/topic/105041801#866 Please...

@TobiasSchaffner : Is this related to misaligned access exception or something else ?

> > We already have a SBI extension proposal close to the final stages. It started with misaligned delegation and expanded to other config behaviors for ISA (ADUE, CFI etc)....