Andrew Waterman
Andrew Waterman
Previously, the cache simulator was basically modeling a multithreaded core, rather than a homogeneous multicore, which is probably more useful. cc @chihminchao
Should be 32b (like fcsr). Not a bug, just an aesthetic concern.
Going forward, we'd like to allocate only a single stateen bit for small extensions defined between priv-spec releases, rather than allocating a bit for every small extension. This isn't an...
No one has been beating down the door requesting changeable XLEN, but since it'll probably happen eventually, I wanted to have a place to take notes on what changes need...
Consider the following scenario: an explicit store to a clean page causes a VS-stage D bit to be set. That VS-stage page table lives on a G-stage page which is...
Following up on a two-year-old message from Grigorios https://lists.riscv.org/g/tech-vector-ext/message/268, we should revisit the sqrt-approximation example in the context of subnormal inputs. There's an accuracy concern, but more problematically, the smallest...
REV8.H is a subset of the more generalized GREVI instruction. We should coalesce around GREVI-based encodings rather than defining one-off encodings for its subsets. So, my recommendation is to remove...
WEXT[I] performs the same function as FSR[I] (RV32) or FSR[I]W (RV64). Zbt is not yet frozen, and so the resolution is somewhat arbitrary. But my recommendation is to delete WEXT[I]...
PKBB16/PKBB32/PKTT16/PKTT32 overlap PACK[U][W] in Zbp. Zbp is not yet frozen, but a subset _is_ frozen: Zbb includes `zext.h`, which maps to `pack[w] rd, rs1, x0`. My recommendation is to retain...