Adrian Siekierka

[65C816, 65CE02] Long branch instructions not supported

2

There's two parts to this: * The compiler is not aware of long branch instructions on 65CE02 (which provides a 16-bit signed variant for every 6502 branch opcode), as well...

Missing G_SBC commutation for equality checks

1

Maybe ```c++ volatile unsigned char * const border_color = (unsigned char *)0xD020; bool foo(unsigned char val) { return *border_color == val; } ``` which emits ``` foo(unsigned char): ; @foo(unsigned...

[6502X] Optimization: multi-byte decrements with DCP

5

Currently, code of the form: ```c long z; z -= 1; ``` compiles to: ``` ldx z dec z cpx #0 bne .LBB0_6 ldx z+1 dec z+1 cpx #0 bne...

The 65CE02 makes STX/STY's orthogonality match LDX/LDY, by virtue of adding STX abs,y and STY abs,x. As such, a variant of STAbsIdx for the 65CE02 could be created which is...

Initial support for building libcxx/libcxxabi on MOS.

3

Starting point for https://github.com/llvm-mos/llvm-mos/issues/198 ; part of https://github.com/llvm-mos/llvm-mos/issues/233 ; probably resolves https://github.com/llvm-mos/llvm-mos-sdk/issues/52 though may need more adaptation work with time. ``` $ mkdir build-libcxx $ cd build-libcxx $ cmake -G...

Memblers of the NESdev forums pointed out the existence of an ASM trick called the "identity table": https://www.nesdev.org/wiki/Identity_table - this uses an identity table (where `LDA table,x` == `x` for...

[65816] 16-bit register mode support

2

Part of https://github.com/llvm-mos/llvm-mos/issues/32 . The main challenge here is being clever about emitting REP/SEP instructions to switch, and deciding which register widths to support and how - while the 8-bit...

[HuC6280] Allow configuring maximum block copy instruction length.

1

Currently, the HuC6280 block copy legalizer (`MOSLegalizerInfo.tryHuCBlockCopy`) conservatively limits the length of a single block copy instruction (`TII`/`TDD`) to 16 bytes. This is because a block copy instruction stalls interrupt...

Xark pointed out that cc65 is capable of a 65C02-specific optimization which llvm-mos does not currently implement: C source: VERA.control = 0; VERA.display.video |= 0b01110000; cc65: stz $9F25 lda #$70...

Compiler/linker-level banking support (Planning)

1

A lot of 6502-based platforms which outgrew the 64K limit (Atari 8-bit cartridges, RAM expansions; Commodore 128; NES/PC Engine cartridges; Commander X16; MEGA65; etc.) provide some means of banking the...