Arun Chandran

> So far I could not see any reliable improvement with --disable_pcie_relaxed in my tests (tried a few different parameters, bw / latency measurements, different transports). The parameter space is...

> @edgargabriel WDYT should be the default setting of UCX_IB_PCI_RELAXED_ORDERING on AMD CPU? @yosefe @edgargabriel I checked this internally, the recommended default value for UCX_IB_PCI_RELAXED_ORDERING on AMD CPUs is "yes"....

@yosefe and @tvegas1, Thank you for your responses. I would like to clarify if the two suggestions provided are identical: a) Implementing a new variant of the rkey_ptr protocol (with...

@yosefe Anything pending on this? Is it good to go?

@yosefe Thanks for the review, I will address the comments.

@yosefe Is there anything pending on this?

> @yosefe Is there anything pending on this? @yosefe @tvegas1 A gentle reminder for the review, is this ready for commit?

> because of the need to support assymetric situations, we cannot assume the other peers would use the same transport. so we use the adaptive progress mechanism in order to...

@yosefe Is the simultaneous polling of two different FIFOs from the shared_memory_interface (sysv, posix, and xpmem) a valid use-case? With my patch, I am seeing the following gtest fail intermittently...

> because of the need to support assymetric situations, we cannot assume the other peers would use the same transport. so we use the adaptive progress mechanism in order to...