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N64: fix SWL/SWR behavior with respect bus accesses
SWL/SWR do a single bus access because SysAD supports 24-bit memory writes: https://n64brew.dev/wiki/SysAD_Interface
Ares emulates them doing multiple 8/16/32 bit accesses. This does not matter most of the times, but it does matter for full accuracy when using SWL/SWR to write RCP address (such as hardware registers or PI bus), given that RCP ignores the access size in those cases causing funny bugs. We do emulate this behavior correctly for LW/SW (see Memory::IO), but this in turns requires the CPU to do the correct bus access, which does not happen for SWL/SWR yet.