apache
sigdeliver/smp: restored registers should be protected by critical section
Summary
sigdeliver/smp: restored registers should be protected by critical section
[CPU1] [24] up_assert: Assertion failed CPU1 at file:armv7-a/arm_sigdeliver.c line: 73 task: waiter [CPU1] [24] arm_registerdump: R0: 00000001 R1: 108321d8 R2: 1081922c R3: 108321d8 [CPU1] [24] arm_registerdump: R4: 10832158 R5: 10817070 R6: 1083a654 FP: 108321d8
Signed-off-by: chao.an [email protected]
Impact
N/A
Testing
sabre-6quad/smp, ostest
@anchao
I've never seen the following DEBUGASSERTION which you described above.
[CPU1] [24] up_assert: Assertion failed CPU1 at file:armv7-a/arm_sigdeliver.c line: 73 task: waiter
Is it possible to reproduce the assertion with sabre-6quad:smp on QEMU?
Hmm, something is wrong with the CI. Let me restart the CI.
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Is it possible to reproduce the assertion with sabre-6quad:smp on QEMU?
Yes, this issue only occurred once during ostest for a long time( 5+ qemu process, about ~12h), crash case is : https://github.com/apache/incubator-nuttx-apps/blob/master/testing/ostest/signest.c#L198 (not sighan)
@anchao
I remember that https://github.com/apache/incubator-nuttx/pull/2960 changed sigdeliver handling for SMP. Do you think that this issue relates to the above PR?
I remember that https://github.com/apache/incubator-nuttx/pull/2960 changed sigdeliver handling for SMP. Do you think that this issue relates to the above PR?
Yes, this PR is related with #2960, but they are resolve different issues.
But I found that this PR does not fix the SMP issue completely, from the debug trace, if CPU0 enter the critical section, CPU1 was still running the current tcb without pause.
CPU 0 -> up_schedule_sigaction() in (critical section)
CPU 1 -> arm_sigdeliver()
CPU 0 -> up_schedule_sigaction() out (critical section)
panic
I will investigate this issue further.