oh_fifo_async: GENERIC target probably doesn't synthesize correctly in Vivado

[olajep]

[olajep]

Missing constraints?

These were extracted from 'fifo_async_104x32'

#------------------------------------------------------------------------------#
#                         Native FIFO Constraints                              #
#------------------------------------------------------------------------------#

# Set false path on the reset synchronizers

set_false_path -through [get_ports rst] -to [get_pins -hierarchical -filter {NAME =~ *rstblk*/*PRE}]
set_false_path -from [get_cells -hierarchical -filter {NAME =~ *rstblk*/*rst_reg_reg[*]}]


set wr_clock          [get_clocks -of_objects [get_ports wr_clk]]
set rd_clock          [get_clocks -of_objects [get_ports rd_clk]]

# Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
set_disable_timing -from CLK -to O [filter [all_fanout -from [get_ports wr_clk] -flat -endpoints_only -only_cells] {PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==LUTRAM}]

# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO

set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].wr_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $rd_clock]

set_max_delay -from [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[*]] -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].rd_stg_inst/Q_reg_reg[*]] -datapath_only [get_property -min PERIOD $wr_clock]
################################################################################

Seems like others have had similar issues: https://github.com/alexforencich/verilog-axis/issues/6