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aolofsson
Verilog library for ASIC and FPGA designers
Updates
Headless tested and working. HDMI bitstream video tested & working (need different device tree). Sound not tested for HDMI design.
Makes master/slave MODE=0 (CPOL=0 CPHA=0) (The master transmitted in CPHA=0 but sampled in CPHA=1, similarly the slave sampled in CPHA=0 but transmitted in CPHA=1) Works around XILINX issue w/ oh_fifo_sync...
With this all Linux kernel interrupt API types are now supported by the driver. Branch with full history here: https://github.com/parallella/parallella-linux/tree/oh-gpio ChangeLog: commit 084e854e045df6161228348f8b442ed90e57bb24 Author: Ola Jeppsson [email protected] Date: Sat May...
Signed-off-by: Peter Saunderson [email protected]
Using elink0_mux_txwr_access to filter frames for elink0 and elink1_mux_rxwr_access for elink1 Tests can write to mailbox in elink0 or elink1 and read from mailbox in elink0 Adding WAIT parameter to...
Antmicro recently released a sphinx domain for Verilog which enables you to write software style documentation for your Verilog / SystemVerilog code. When you combined it with a few other...
