Fluent10g bitstream generation fails

[harshgondaliya]

I am following the steps mentioned on this page to do the hardware and software setup for Fluent10G. The bitstream generation step fails giving the below-mentioned output. make -C $FLUENT10G/src hw

INFO: [IP_Flow 19-861] XGUI layout file basename "xgui/nt_timestamp_top_v1_0.tcl" does not have the current IP <name>_v<version> format. If the IP name or version was changed recently, recreate this file to update the file format.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [Ipptcl 7-1486] check_integrity: Integrity check passed.
## ipx::save_core [ipx::current_core]
## close_project
INFO: [Common 17-206] Exiting Vivado at Sat Aug 15 17:06:13 2020...
make[2]: Leaving directory '/scratch/netfpga/fluent10g/src/hardware/ip/nt_timestamp'
make[1]: Leaving directory '/scratch/netfpga/fluent10g/src/hardware'
make -C hardware/ project
make[1]: Entering directory '/scratch/netfpga/fluent10g/src/hardware'
if ! test -f ip/nt_10g_if/component.xml; then\
	echo "ERROR: please create nt_10g_if ip core first";\
elif ! test -f ip/nt_10g_if_shared/component.xml; then\
	echo "ERROR: please create nt_10g_if_shared ip core first";\
elif ! test -f ip/nt_ctrl/component.xml; then\
	echo "ERROR: please create nt_ctrl ip core first";\
elif ! test -f ip/nt_datarate/component.xml; then\
	echo "ERROR: please create nt_datarate ip core first";\
elif ! test -f ip/nt_gen_rate_ctrl/component.xml; then\
	echo "ERROR: please create nt_gen_rate_ctrl ip core first";\
elif ! test -f ip/nt_gen_replay/component.xml; then\
	echo "ERROR: please create nt_gen_replay ip core first";\
elif ! test -f ip/nt_gen_timestamp_insert/component.xml; then\
	echo "ERROR: please create nt_gen_timestamp_insert ip core first";\
elif ! test -f ip/nt_ident/component.xml; then\
	echo "ERROR: please create nt_ident ip core first";\
elif ! test -f ip/nt_packet_counter/component.xml; then\
	echo "ERROR: please create nt_packet_counter ip core first";\
elif ! test -f ip/nt_recv_capture/component.xml; then\
	echo "ERROR: please create nt_recv_capture ip core first";\
elif ! test -f ip/nt_recv_filter_mac/component.xml; then\
	echo "ERROR: please create nt_recv_filter_mac ip core first";\
elif ! test -f ip/nt_recv_interpackettime/component.xml; then\
	echo "ERROR: please create nt_recv_interpackettime ip core first";\
elif ! test -f ip/nt_recv_latency/component.xml; then\
	echo "ERROR: please create nt_recv_latency ip core first";\
elif ! test -f ip/nt_timestamp/component.xml; then\
	echo "ERROR: please create nt_timestamp ip core first";\
elif test -d project; then\
	echo "ERROR: project already exists";\
else \
	vivado -mode batch -source tcl/fluent10g_create.tcl;\
fi;\

ERROR: please create nt_gen_rate_ctrl ip core first
make[1]: Leaving directory '/scratch/netfpga/fluent10g/src/hardware'
make -C hardware/ synth
make[1]: Entering directory '/scratch/netfpga/fluent10g/src/hardware'
if ! test -d project/; then\
	echo "ERROR: project does not exist";\
fi;\
vivado -mode batch -source tcl/fluent10g_synth.tcl
ERROR: project does not exist

****** Vivado v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
  **** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source tcl/fluent10g_synth.tcl
# set design fluent10g
# set proj_dir ./project
# open_project ./${proj_dir}/${design}.xpr
ERROR: [Coretcl 2-27] Can't find specified project.
INFO: [Common 17-206] Exiting Vivado at Sat Aug 15 17:06:24 2020...
Makefile:81: recipe for target 'synth' failed
make[1]: *** [synth] Error 1
make[1]: Leaving directory '/scratch/netfpga/fluent10g/src/hardware'
Makefile:38: recipe for target 'hw' failed
make: *** [hw] Error 2
make: Leaving directory '/scratch/netfpga/fluent10g/src'
root@godel:/scratch/netfpga/fluent10g/src# 

[anmomu92]

Maybe you could try installing Vivado version 2018.3. It solved that issue in my case