Issue in simulating only processor(core.vhdl) in vivado

[sasi8985]

I wanted to simulate the core to view wave forms of different instructions. But i am struck. I am getting this error "FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support."

I created a System Verilog testbench file and instantiated core.vhdl first to see whether at least clock runs or not at my end but i got above error. I am attaching log files. xvhdl.log xvlog.log elaborate.log webtalk.log compile.log Tcl_console_output.txt

Here is the code : -

`

`timescale 1ns/1ns
typedef struct packed { longint dat;
                                      bit ack;
                                      bit stall;} wish_slave_out ;
                    
typedef struct packed { longint dat;
                                      int addr;
                                      byte sel; 
                                      bit cyc;
                                      bit stb;
                                      bit we; } wish_master_out ;

module top_u ;

bit clk=1,rst=1,rst_1,dmi_req,dmi_ack,dmi_wr,ext_irq,terminated_out;
bit [3:0] dmi_addr;
longint dmi_din,dmi_dout;

wish_slave_out s_insn_in,s_data_in;
wish_master_out m_insn_out,m_data_out; 

parameter bit [63:0]alt_addr = '{64{0}};

core#(0,0,1,alt_addr,512) a1 (.clk(clk),.rst(rst),.alt_reset(rst_1),.wishbone_insn_in(s_insn_in),.wishbone_insn_out(m_insn_out),
                            .wishbone_data_in(s_data_in),.wishbone_data_out(m_data_out),.dmi_addr(dmi_addr),.dmi_din(dmi_din),
                            .dmi_dout(dmi_dout),.dmi_req(dmi_req),
                            .dmi_wr(dmi_wr),.dmi_ack(dmi_ack),.ext_irq(ext_irq),.terminated_out(terminated_out) );
                                                       
     initial
        begin
            repeat(1000)
                begin
                    #100 clk = ~clk;
                end
        end
     
     initial
        begin
            #200 rst = 0;
        end
          
     initial
        begin
            $dumpfile("dump.vcd");
            $dumpvars(0,top_u);
        end                      
                          

endmodule

` Also i wanted to know if there is an SV verification requirement. Thanks in advance

[umarcor]

Vivado Simulator does not support several features of VHDL 2008 and it's lacking some of VHDL 1993. Therefore, it's better to use any other simulator with proper language support. See #242.

Alternatively, you can try converting the sources to Verilog through ghdl --synth. See https://ghdl.github.io/ghdl/using/Synthesis.html#cmdoption-ghdl-out.