fastvdma

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Documentation for use as AXI4 Stream target

5

Hi, Is there/can you provide documentation on how to use the DMA Controller as a target for an AXI4-Stream. In this case, I am using the DMA controller in Renode....

p-owens

Seee https://www.grammarly.com/blog/busses-buses/

hughperkins

Trying to change read interface to AXI4, getting elaboration errors when generating verilog

2

Steps to recreate: 1. Have dependencies installed (sbt, jdk, scala), clone fastvdma repo, and navigate to the cloned repo directory. 2. Make the following edits: File: src/main/scala/DMAController/DMATop.scala Line 36: ```...

seandextercrevinn

Is fastvdma tested on rocketchip?

1

> FastVDMA was verified in the xc7z030fbg676-2 chip hi, is Fastcdma tested on rocketchip?

meton-robean

Port to Chisel 6.x

1

This PR contains 2 separate changes: - Upgrade to Chisel 6.0.0 - Port build system from `sbt` to `mill` I have only done very limited simulation test on the changes....

kammoh

Any example design in Vivado?

1

Is there any example/reference design uploaded somewhere for Vivado or any other platforms? I am having issues with memory mapped addressing in Vivado and I wanted to figure out if...

nuclearrambo