[Verilog] Issue with Verilog specify block and polarity operator

[thechickenundertheroad]

When inside a specify block with a parallel_path_description the parser incorrectly handles a +: or -: This is because the +/-: is a defined operator in the Lexer. The polarity_operator defined inside the parser is not taking precedence over the lexer. +: should be taken as a polarity operator followed by a colon and not just PLCL

[msagca]

Hi @thechickenundertheroad,

PLCL (+:) defined in the lexer is for range expressions. It would make no sense to produce two distinct tokens (+ and :) for this operator.

There is no rule in the grammar that would cause a +: or -: take precedence over a polarity_operator followed by :. They are used in different context.