systemc-clang
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anikau31
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
# Description The state machine for `threadProc()` thread in [test_const_prop_loop.cpp](https://github.com/intel/systemc-compiler/blob/main/tests/method/test_const_prop_loop.cpp#L67) contains `hIfStmt` node that has `hCStmt NONAME NOLIST` as its condition. The `threadProc()` thread: ```c++ void threadProc() { unsigned slot...
It seems that the options for `run-compare.py` have some dependencies that are not intuitive. The example below works fine (taken from the add example). ``` python3 -B $SYSTEMC_CLANG/tests/verilog-conversion/run-compare.py \ hdl-to-v...
# Description The matcher for code arrays of signals, ports and submodules is quite similar. It is possible to refactor the code to use the same matcher code.
# Description The destruction of objects with `Matchers` and `SystemCClang` should be revisited. It seems that the destruction of dynamically objects are not done properly.
# Description Use include-what-you-use into the project to determine which include files must be included and others can use forward declarations. This is an enhancement to try and improve the...
Ideally, Verilog conversion golden data and Verilog tests should be in the same folder and both should be in an external module.
# Description The script for running the Verilog conversion and the convert.py is fixed and is the `tests/verilog-conversion/run-compare.py`. However, convert.py requires changes to correctly convert `_hdl.txt` into Verilog.
TL;DR: in `scratch-clang19` branch, the unimpl test fails, and hUnimpl nodes are generated in _hdl.txt for z3test.cpp The command to produce the _hdl.txt file: `/systemc-clang-build/systemc-clang /systemc-clang/examples/llnl-examples/zfpsynth/zfp3/z3test.cpp -- -x c++ -w...
# Description I'm trying to run behavioral simulation for ZHW on fccm-ae branch using target test_z3_behav. ``` make test_z3_behav ERROR: [Vivado 12-172] File or Directory '/home3/shared/liu91/systemc-clang/hardware/build/verif/../rtl/sysc_z3test.sv' does not exist '/home3/shared/liu91/systemc-clang/hardware/build/verif/../rtl/sysc_z3test.sv'...
# Description Remove deprecated code on SupplementaryInfo in SplitCFG that was used to store only the first block ID on the false path. It has been superseded by the PathInfo....