Instantiation of array of module

[zhuanhao-wu]

In Vivado (as of 2022.1), there are two ways where we could generate an array of modules as shown below.

• The top_generate shows one way where we translate the declaration of an array of modules into a generate block, and translate port binding in another generate block. This way we don't need to unroll the for-loop.
• The top_array shows another way where the modules can be declared as an array. However, catch is that for-loop will not work as in the top_generate example, because slicing an array of modules is not supported in Vivado. A workaround would be to generate separate wires with proper width and the for loop will act on the generated wires.

// array of dff modules
module dff(
  input clk,
  input d_i,
  output reg d_o
);
  always @(posedge clk) begin
    d_o <= d_i;
  end
endmodule

// option 1 is supported
module top_generate(
  input wire clk,
  input wire[15:0] d_i,
  output wire[15:0] d_o
);
  genvar i;
  /* the module declaration should be instantiate as follows */
  generate
  for(i = 0; i < 8; i = i + 1) begin : dff_array
    dff inst(

    );
  end
  endgenerate

  generate
  for(i = 0; i < 8; i = i + 1) begin : dff_bind
    assign dff_array[i].inst.clk = clk;
    assign dff_array[i].inst.d_i = d_i[i];
    assign d_o[i] = dff_array[i].inst.d_o;
  end
  endgenerate

endmodule

// option 2 is closer to the semantics of the C++, but is not supported
module top_array(
  input wire clk,
  input wire[7:0] d_i,
  output wire[7:0] d_o
);
  dff dff_array[7:0] (
    /* the following approach is possible, but not suitable for our case
    * as it requires matching width
     .clk(clk),
     .d_i(d_i),
     .d_o(d_o) */
  );
  // genvar i;
  // generate
  // for(i = 0; i < 8; i = i + 1) begin : dff_bind
  //    dff_array[i].clk = clk;
  //    dff_array[i].d_i = d_i[i];
  //    d_o[i] = dff_array[i].d_o;
  // end
  // endgenerate

endmodule