aneshlya
aneshlya
> Why compat[CPU_ZNVER2] don't include CPU_ZNVER1 [here](https://github.com/ispc/ispc/blob/b8b8bf8b685852f6719abbc2d47e9d11651730c9/src/ispc.cpp#L657)? Same question with compat[CPU_ZNVER3] and CPU_ZNVER2. This looks like a bug to me.
> I wonder if m_hasIntelVNNI might enable 256-bit instructions and causes issue, especially if disableZMM is set. I do not have an IceLake CPU to test that carefully. `avx512icl-x16` target...
Yes, ISPC enforces a vector width of 256 for this target, and you're correct—this choice is made to better accommodate smaller data types. However, we could consider introducing an option...
Proper implementation of the `avx512_x8` targets with configurable `enable_zmm` / `disable_zmm` options requires introducing a separate internal target within ISPC (not exposed to the user, but used under the hood)....
Hey @matpow2 , did the workaround help? If no, we can add the option to always enable blend stores (ispc already has similar option for Xe targets).
I think it would be beneficial to merge our example with attention algorithm. @nurmukhametov, could you remind me the name of the branch with your latest changes? I'll combine everything...
Perhaps the simplest approach would be to store the original `Symbol` that the `ConstExpr` was optimized from within the `ConstExpr` class itself, and then perform the appropriate checks in the...
> Expected behavior: produce error and exit nicely. Actually, it's totally valid code. The compiler should compile it successfully.
Here is a repro: https://godbolt.org/z/991h19EEd
@nurmukhametov , can it be closed?