ADL 100% Machine_Clears

[andikleen]

@aayasin This is with the TMA 4.7 update: 100% Machine clears can't be right? It's fairly reproducible.

$ ./toplev -l7 -Sq ./workloads/PERL1s

4.7-full, 2.0 on 12th Gen Intel(R) Core(TM) i7-1270P [adl]

core FE Frontend_Bound.Fetch_Latency.Branch_Resteers.Clears_Resteers % Clocks 0.0 core BAD Bad_Speculation.Machine_Clears % Slots 100.0 <== core FE Frontend_Bound.Fetch_Latency.MS_Switches % Clocks_est 0.0 core RET Retiring.Heavy_Operations.Microcode_Sequencer % Slots 0.0 core BAD Bad_Speculation % Slots 100.0 core BE/Mem Backend_Bound.Memory_Bound.L1_Bound % Stalls 0.0 core BE/Mem Backend_Bound.Memory_Bound.L3_Bound.Contested_Accesses % Clocks_est 0.0 core BE/Mem Backend_Bound.Memory_Bound.L3_Bound.Data_Sharing % Clocks_est 0.0 core BE/Mem Backend_Bound.Memory_Bound.Store_Bound.False_Sharing % Clocks_est 0.0 core BE/Core Backend_Bound.Core_Bound.Ports_Utilization.Ports_Utilized_1 % Clocks 0.0