no-OS ADF4368 driver - Cannot lock PLL using the example

I started porting the driver of ADF4368 for Zephyr RTOS starting form this file adf4368.c (yes, I have converted some no_OS things into Zephyr ones). During the porting I've also fixed some typos like

ret = adf4368_spi_update_bits(dev, 0x35, ADF4368_DCLK_MODE_MSK, 0xff); // address correct (line 1829)
if (ret)
	return ret;

ret = adf4368_spi_update_bits(dev, 0x35, ADF4368_EN_ADC_CLK_MSK, 0xff); // adress is 0x31 from datasheet (line 1833)
if (ret)
	return ret;

After this work i wanted to use the driver as the example, see the adf4368_init function in the example: basic_example.c

I have configured all parameters in the same order of the driver and used the same function call order but the PLL does not lock.
Then i refactored the code to do the minimum needed things without improvement. I'm stuck at failing the "check lock detector" of the pll (in the set_freqfunction) and i wait the double of the lock time. No LD LED lights up.
Also I have improved the set_freq by adding a check on ADC_BUSY and FSM_BUSY bits (see datasheet). The check pass.
I also added a fix for PD_ALL and PD_LD not unset during set_freq. Maybe I'm wrong with "when" unset these bits.
final step: using ACE with the evb
- set up the evb working with ace
- collect the registers
- setup spi connection
  - reg 0x00 for SPI config
  - set the 3v3 in another register
- reg 0x2F for REF settings (one time I have checked the REF_OK bit unsetting PD_RDET first)
- send some of theese register to the PLL
  - 0x00000010
  - 0x00000011
  - 0x00000012
  - 0x00000013
  - 0x00000014
  - 0x00000015
  - 0x00000016
  - 0x00000017
  - 0x00000018
  - 0x00000019
  - 0x0000001A
  - 0x0000001B
  - 0x0000001C
  - 0x0000001D
  - 0x0000001E
  - 0x0000001F
  - 0x00000020
  - 0x00000021
  - 0x00000022
  - 0x00000023
  - 0x00000024
  - 0x00000025
  - 0x00000026
  - 0x00000027
  - 0x00000028
  - 0x00000029
  - 0x0000002A
  - 0x0000002B
  - 0x0000002C
  - 0x0000002D
  - 0x0000002E
  - 0x0000002F
  - 0x00000030
  - 0x00000031
  - 0x00000035
  - 0x00000036
  - 0x00000037
  - 0x00000038
  - 0x00000039
  - 0x0000003A
  - 0x0000003B
  - 0x0000003E
  - 0x0000003F
  - 0x00000040
  - 0x00000043
  - 0x0000004E
  - 0x00000053
  - 0x00000054
- PLL locks
- using simplified set_freq to change freq
- PLL change freqeuency and locks

Maybe someone want to take a look on this. I think I need some suggestion on how to proceed further. Thanks in advance for your help.

Aug 21 '25 15:08 pstz9x

Hi @pstz9x ,

What hardware do you use ? MCU eval board connected to ADF4368 eval board ?

What clock reference ?

What's the target VCO frequency ?

Can you share the code where you initialize the adf4368 ?

One last thing, whenever I have a working setup (like the ACE setup you mention), I usually do a register dump on it, and then a register dump in my work-in-progress code and see the differences immediately.

Aug 26 '25 09:08 buha

Hi @buha thanks for the questions.

Custom PCB: MCU connected to ADF4368 (I also tried MCU eval board + ADF4368 eval board for the first part, but for now I can't use this setup for a while)
Custom PCB has 100MHz f_REF differential input LVDS
- PLL lock at near 10GHz if ACE register for 11GHz are written; Seems a good starting point because the set_freq then is usable to change frequency correctly
target freq will be between 5 to 8 GHz but I want to try the 10 and the 10.6 GHz as in ACE default configuration

For the last question and the register dump comparison I need some time to collect the info.

Aug 26 '25 09:08 pstz9x