analogdevicesinc
[Doc] New section regarding Intel projects workflow
PR Description
New page that describes the workflow used in building the HDL Intel projects & the files that are involved in the process. This page is just a prototype, one more project needs to be included (Stratix10), but only after the major changes are made, if there will be any.
PR Type
- [ ] Bug fix (change that fixes an issue)
- [ ] New feature (change that adds new functionality)
- [ ] Breaking change (has dependencies in other repos or will cause CI to fail)
PR Checklist
- [x] I have followed the code style guidelines
- [x] I have performed a self-review of changes
- [ ] I have compiled all hdl projects and libraries affected by this PR
- [ ] I have tested in hardware affected projects, at least on relevant boards
- [ ] I have commented my code, at least hard-to-understand parts
- [x] I have signed off all commits from this PR
- [x] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
- [ ] I have not introduced new Warnings/Critical Warnings on compilation
- [ ] I have added new hdl testbenches or updated existing ones
V2: Did the requested changes, left the FPGA name's tag unchanged until we have a final version of this page.
V4: Addressed the last issues mentioned in the PR. The typos were fixed. Regarding the rest of the comments, about the files & branches needed in the build process, I added several sections (like warning and cautions) to explain to the user that these tutorials used the available resources at that time and the user needs to make sure is responsible for the Quartus version and the branch for the u-boot image. The workflow remains the same & it's recommended to use the recent versions of Quartus.
The rebase with main will be made when we agree on the other issues. Left unresolved the issues were there are still doubts.