hdl
hdl copied to clipboard
spi_engine: scripts: Fix offload clock domain
PR Description
At the configuration instantiated by the script, ctrl_clk and spi_clk are always synchronous. When axi_spi_engine/ASYNC_SPI_CLK=1, the ctrl_offload intf is fully domain crossed from clk to spi_clk. Thus, spi_engine_offload/ASYNC_SPI_CLK=0.
The projects that use spi_engine_create on main are
projects/ad4134_fmc/common/ad4134_bd.tcl
projects/ad4630_fmc/common/ad463x_bd.tcl
projects/ad4630_fmc/common/ad463x_bd.tcl
projects/ad469x_fmc/common/ad469x_bd.tcl
projects/ad7134_fmc/common/ad7134_bd.tcl
projects/ad738x_fmc/common/ad738x_bd.tcl
projects/ad7606x_fmc/common/ad7606x_bd.tcl
projects/ad7616_sdz/common/ad7616_bd.tcl
projects/adaq7980_sdz/common/adaq7980_bd.tcl
projects/cn0363/common/cn0363_bd.tcl
projects/cn0540/common/cn0540_bd.tcl
projects/cn0561/common/cn0561_bd.tcl
projects/pulsar_adc/common/pulsar_adc_bd.tcl
And none overwrites the spi_clk, ctrl_clk driving the offload. Tested on HW with the ad77681evb project from the dev_adaq7768 branch rebased to main.
The motivation of this change is to reduce the offload trigger minimum interval.
PR Type
- [X] Bug fix (change that fixes an issue)
- [ ] New feature (change that adds new functionality)
- [ ] Breaking change (has dependencies in other repos or will cause CI to fail)
PR Checklist
- [X] I have followed the code style guidelines
- [X] I have performed a self-review of changes
- [ ] I have compiled all hdl projects and libraries affected by this PR
- [X] I have tested in hardware affected projects, at least on relevant boards
- [ ] I have commented my code, at least hard-to-understand parts
- [X] I have signed off all commits from this PR
- [ ] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
- [ ] I have not introduced new Warnings/Critical Warnings on compilation
- [ ] I have added new hdl testbenches or updated existing ones