AD7606B: Add support for Parallel ADC Read Mode

[alin724]

AD7606B: Add support for Parallel ADC Read Mode:

• axi_ad7606b module

• ad7606b project

[alin724]

V2:

• Removed the rx_cnvst_n signal from axi_ad7606b IP, this being generated using axi_pwm_gen module;

[alin724]

V3:

• axi_ad7606b IP: Updated up_adc_common and channel instances with raw data reading and register data reading/writing features;
• ad7606b_fmc project: Defined missing pins;

[alin724]

V4:

• Rebased to the master branch;

[alin724]

V5:

• Updated to latest up_adc_channel read raw data functionality version;

[alin724]

V6:

• Rebased to the master branch;

[AndreiGrozav]

Run hdlmake script, to update the makefiles.

[alin724]

V7:

• Updated makefiles;

[AndreiGrozav]

In the .log file you get a few CRITICAL warnings. CRITICAL WARNING: [Common 17-55] 'get_property' expects at least one object. [/media/data/github/dev/hdl_ad7606/projects/ad7606b_fmc/zed/ad7606b_fmc_zed.gen/sources_1/bd/system/ip/system_axi_ad7606b_dma_0/system_axi_ad7606b_dma_0_constr.xdc:32

This happens when an input clock is not defined. This is not the case here. The tool should figure out that you are using the ps 0 clock. Leaving things like this will mess wit our continuous integration flow, so it has to be fix. Add a clock constraint on the output clock of the ad7606. that will let the tool know is the same 100MHz clock Maybe something like, with device by 1: https://github.com/analogdevicesinc/hdl/blob/master/projects/ad_quadmxfe1_ebz/vcu118/timing_constr.xdc#L13

[alin724]

V8:

• Updated project's GPIO pins;
• Used generated 100MHz clock from cpu_clk as an external_clk. Generated for axi_dmac and up_cpack2 modules' clocks ,instead of axi_ad7606b's adc_clk;

[alin724]

V9:

• renamed ext_clk bus in axi_ad7606b_ip.tcl definition fiel to external_clk;

Notes:

• Software must control the adc_reset pin of AD7606B;
• Recommended mode of operation using adc_os pins: software mode ('b111) - all operation modes will be able to be used in this case;

[alin724]

V10:

• axi_ad7606b: Update up_adc_common and up_adc_channel instances;

[alin724]

V11:

• HDL driver for parallel interface of the AD7606x family devices: AD7606B and AD7606C-16 in ad7606x_16b_pif.v and AD7606C-18 in ad7606x_18b_pif.v;
• AD7606X HDL Reference Design in ad7606x_fmc;

[alin724]

V12:

• Added new operation mode: CRC computing option using data bits, status header bits and zeros;

[alin724]

V13:

• Added missing CRC_STATUS parameter in axi_ad7606x_16b_pif and *_18b_pif modules;
• Updated axi_ad7606x_ip.tcl file;

[alin724]

V14:

• Added Readme.md file to the project's directory;

[alin724]

V15:

• (axi_ad7606x) Added support for the new ADC config mechanism;
• (ad7606x_fmc project) Added EXT_CLK parameter;

[alin724]

V16:

• Remove redundant code related to the parameters setup in the system_project.tcl file;

[alin724]

V17:

• Updated license header to current year;
• Updated ad_datafmt instances to use axi_ad7606x's module parameters;

[alin724]

V18:

• Updated read_ch_data signal conditions in the pif's modules;

[alin724]

V19:

• (axi_ad7606x) Updated indentation in axi_ad7606x_18b_pif module;
• (ad7606x_fmc_zed) Updated system_id's "custom string" field;