Ensure all allowed filter bit combinations can be set on on AD7124.

[robste1987]

If the parameter of AD7124_FILT_REG_FS() was changed from 384, it was unlikely to be transferred to the AD7124 properly. This made it impossible to change the output data rate of the ADC.

Root cause is that all filter registers have a Power-On/Reset Value of 0x060180, which means that FS is 0x180 (=384) by default. Instead of replacing the default value by the paramter of AD7124_FILT_REG_FS(), the default value and the paramter were binary anded and the result was written into the FS bits.

Solution is to build up the new register content from 0. It ensures the default POST_FILTER setting is kept if not expilicitly changed. The REJ60 and SINGLE_CYCLE bits stay clear as they are in Power-On/Reset. This is considered okay because this code is intended to initialize the AD7124 after a power-on or reset.