Add CRC generator

[adamgreig]

This PR adds a CRC generator to the stdlib. It supports the full set of Williams/Rocksoft model parameters, which in practice means it should be able to generate and validate pretty much every commonly used CRC directly, and significantly that includes all the ones in the reveng catalogue and crcmod predefined list.

It's configurable for arbitrary input word widths with a constant single-cycle latency, so can be used to generate a classic bit-at-a-time shift-register CRC, or update wider words in parallel. It doesn't support masking the input words, which might limit its use in very wide masked data paths, though I expect that could be added later in a backwards-compatible way if necessary. I haven't thought about how masking might be implemented.

The generated logic is a product/XOR equation for each bit of the new state which includes bits of the previous state and current input. As far as I'm aware this is essentially the best way to generate an arbitrary parallel CRC in hardware.

Currently it uses a reset and valid input signal, rather than e.g. relying on users to add EnableInserter and ResetInserter as appropriate. I don't know what the preferred way to deal with that is in stdlib items. Since reset will pretty much always be required it seems easier to have it as an input than requiring ResetInserter; I guess some applications may never need to change valid if they always have valid new data after resetting.

The test suite uses a variety of standard CRCs to provide coverage of the various input parameters, and tests each at input word widths of 1, 2, 4, 8, 16, 32, and 64 bits.

I originally wrote this code for my work, where we've used it in a variety of applications, but I have permission to release it under the BSD two-clause licence for inclusion in Amaranth.