Memory read port data uninitialized and not resettable

[epkRichi]

I was using some Amaranth code that I had exported to Verilog in another project and I noticed that my simulator was showing some undefined (x) values. I traced it back and found out that the lib.memory.Memory read_port__data signal is driven by a register that does not get initialized or reset:

reg [31:0] _0_;
always @(posedge clk) begin
  if (read_port__en) begin
    _0_ <= memory[addr];
  end
end
assign rdata = _0_;
assign read_port__data = rdata;

Here's a playground example

The signal is initialized in the Amaranth simulator, but I dont think it resettable there either as my top module doesn't even have a rst signal apparently.

Is this supposed to be like that? Seems very unusual to me.

[whitequark]

cc @wanda-phi