Alyssa Rosenzweig
Alyssa Rosenzweig
I'm not able to reproduce this... if anyone else can, please comment!
The problem is the `VInsertElement` instructions that are inserted for scalar-vector ops. This "fixes" the issue and generates the ideal assembly: ```diff diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 33a88a147..9f6e13fcc 100644 ---...
Although actually maybe that's ok, because StoreRegister is supposed to mask anyway? or there's no masking that's expected to happen at all? or....... I don't really know what's happening here.
> > please summarize your proposal here > > Sorry, I'm not familiar enough with things to be able to offer any concrete proposals. I just came across this issue...
My FEX repo's zig/cc branch has a proof of concept of building with x86_64 thunks with zig cc on fedora 39, no special rootfs's etc. glxgears works, so far no...
> For Fedora, I wonder if there'd be any problems if we just ask the user to create a separate installroot for the guest libs? So just build the guest...
it might be more consistent with ALU to put a `.sx` source modifier on the offset when signed-extended (and nothing for not)? I really need to RiIR the disassembler ngl
While at it, does it make sense to also add aliases for andn1, andn2, orn1, and orn2?
1. Uniform passed to lod_min is the minimum LOD use as a clamp. 2. With the traditional "binding table" path, there are dedicated "texture state" and "sampler state" registers which...